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Video ICs Dual-line serial control sound processor IC BH3866AS The BH3866AS is a signal processing IC developed for the control of volume and tone quality in TV equipment. Since dual-line serial control (I2C BUS) is used, the volume level and tone quality in TV equipment can be changed using signals such as those from a microcomputer or similar device. *Applications computers, high-vision TVs, karaoke sets, digital broadcasts, CATVs, and other TV equipment DVDs, personal *Features volume and sound quality control (for 1) 3-channel stereo and center speakers). 2) Absorption of volume deviation between input sources and improved S / N ratio, for better sound quality, using an AGC circuit. 3) Control through I2C BUS serial control. 4) Internal pseudo-stereo circuit provides phase-shift matrix surround effect. *Absolute maximum ratings (Ta = 25C) Parameter Power supply voltage Power dissipation Operating temperature Storage temperature Symbol VCC Pd Topr Tstg Limits 10.0 1250 - 25 ~ + 75 - 55 ~ + 125 Unit V mW C C Reduced by 12.5mW for each increase in Ta of 1C over 25C. *Recommended operating conditions (Ta = 25C) Parameter Power supply voltage Symbol VCC Min. 7.0 Typ. -- Max. 9.5 Unit V 1 Video ICs BH3866AS *Block diagram BGAIN MSIN ADD 32 31 30 29 28 27 26 10k - 25 MIX OFF BASS 24 23 22 21 20 19 18 SCV COUT STT LOUT VCC CB CIN CT BIN LB LIN LT 17 VCC 50k CIN L+R 10k - Volume Volume 50k CSEL OFF MIX ON Tone (bass / treble) + - SMON + 50k - 10k ON + 50k + - - OFF Increment AGC Volume Volume 10k L+S VCA ON Tone (bass / treble) + - 10k A G C OFF L+R PHASE Surr effect LFP + OFF ON 10k L-R ON 10k SHIFT - Increment Volume 50k OFF ON LOOP VCC - 50k 50k 1 2 VCC 1 RIN 2 GND 3 AGCADJ 4 LS1 5 LS2 6 SOUT 7 PS 8 Vref 9 STB 10 RT 11 RB 12 ROUT *Pin descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name RIN GND AGCADJ LS1 LS2 SOUT PS Vref STB RT RB ROUT SRV SLV SCL SDA Rch input Ground AGC 0dB adjustment AGC level sensor 1 AGC level sensor 2 Sch output pin and LPF Phase shift pin (internal resistance: 18k) 1 / 2 VCC Bass shock sound integration Rch Treble fc setting Rch Bass fc setting Rch output Vol Rch shock sound integration Vol Lch shock sound integration I2C communications clock Function Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin name DAC SCV COUT LOUT CB CT LB LT STT BGAIN MSIN BIN ADD CIN VCC LIN Function Expansion DAC (L / H) Vol Cch shock sound integration Cch output Lch output Cch Bass fc setting Cch Treble fc setting Lch Bass fc setting Lch Treble fc setting Treble shock sound integration Bass Mix Gain adjustment Mono Sur input Bass detection LPF operating amplifier input L + R added output after AGC Cch input Power supply, 9V Lch input I2C communications data 2 SRV SDA SCL SLV + VCA R-S (bass / treble) - Tone Volume SSTE AMP SON 10k I2C BUS interface SCL SDA 13 14 15 16 DAC + + + + - Video ICs BH3866AS *Input / output circuits Pin No. Pin name Pin voltage Zin I/O VCC Equivalent circuit Function 1 30 32 RIN CIN LIN GND 4.5V 50k I 50k Input pins. 1 2 VCC VCC 200 12 19 20 ROUT COUT LOUT 200 4.5V -- O 10k Output pins. GND VCC 3 AGCADJ -- -- I AGC 0dB adjustment pin. This pin is connected to the base of PNP. The current output from this pin is 1A (Typ.) Max. GND VCC 200 4 LS1 -- -- -- 430 2k Time constant pin on the side that suppresses the AGC signal level. GND 3 Video ICs BH3866AS Pin No. Pin name Pin voltage Zin I/O VCC Equivalent circuit Function 200 5 LS2 -- -- -- 20k 2k Time constant pin on the side that amplifies the AGC signal level. GND VCC 200 10k 6 SOUT 4.5V 10k O Serves as both the output pin for the surround and pseudostereo effects, and the LPF pin. GND 200 VCC 10k 10k 18k 7 PS -- -- -- 18k For the phase-shifter filter for the surround and pseudostereo effects. GND VCC 50k 8 Vref 4.5V -- -- 50k GND 1 / 2 VCC. This voltage serves as the power supply for the signal system. 4 Video ICs BH3866AS Pin No. Pin name Pin voltage Zin I/O VCC Equivalent circuit Function 9 25 STB -- STT 30k DAC GND 30k -- Integration pins that prevent shock sound when switching the bass and treble levels. VCC 10 22 24 RT CT LT GND 4.5V 30k -- 30k Treble filter pins for the left, right, and center channels. 1 2 VCC VCC 11 21 23 RB CB LB GND 4.5V 30k -- 30k Bass filter pins for the left, right, and center channels. 1 2 VCC VCC 13 14 18 SRV SLV SCV -- 30k -- 30k DAC GND Integration pins that prevent shock sound when switching the volume levels on the left, right, and center channels. 5 Video ICs Pin No. Pin name Pin voltage Zin I/O VCC BH3866AS Equivalent circuit Function 15 SCL -- -- I SCL pin for the I2C BUS. This is the clock pin. GND VCC 16 SDA -- -- I SDA pin for the I2C BUS. The Acknowledge signal is output from this pin. This is the data pin. control logic GND VCC 200 17 DAC 0/5 -- O 100k 74.6k 0V and 5V output pin that enables control with the I2C BUS. 25.6k GND VCC BIN 10k 26 BGAIN 4.5V -- -- 50k Gain adjustment pin used to mix the bass on the left and right channels. GND 1 2 VCC 6 Video ICs Pin No. Pin name Pin voltage Zin I/O VCC BH3866AS Equivalent circuit Function 27 MSIN 4.5V 50k I 50k Surround input section for monaural signals in the surround section. 1 2 VCC GND VCC BGAIN 28 BIN 4.5V 50k I 50k Bass signal input to the left and right channels. 1 2 VCC GND VCC 200 29 ADD 4.5V -- O 10k Incremented output from the left and right channels following AGC. 10k 1 2 VCC 200 GND 31 VCC 9V -- -- -- Power supply pin. 2 GND 0V -- -- -- Ground pin. 7 Video ICs BH3866AS *Electrical characteristics (unless otherwise noted, Ta = 25C, VCC = 9V, f = 1kHz, Rg = 600, RL = 10k) Parameter Quiescent circuit current Max. output voltage, Rch Max. output voltage, Lch Max. output voltage, Cch Voltage gain, Rch Voltage gain, Lch Voltage gain, Cch Total harmonic distortion, Rch Total harmonic distortion, Lch Total harmonic distortion, Cch Output noise voltage, Rch Output noise voltage, Lch Output noise voltage, Cch Residual noise voltage, Rch Residual noise voltage, Lch Residual noise voltage, Cch Crosstalk, RchLch Crosstalk, RchCch Crosstalk, LchRch Crosstalk, LchCch Crosstalk, CchRch Crosstalk, CchLch Input impedance, Rch Input impedance, Lch Input impedance, Cch Output impedance, Rch Output impedance, Lch Output impedance, Cch Ripple rejection, Rch Ripple rejection, Lch Ripple rejection, Cch Muting level, Rch Muting level, Lch Muting level, Cch Symbol IQ VOMR VOML VOMC GVR GVL GVC THDR THDL THDC VNOR VNOL VNOC VMNOR VMNOL VMNOC CTR-L CTR-C CTL-R CTL-C CTC-R CTC-L RINR RINL RINC ROUTR ROUTL ROUTC RRR RRL RRC VMUTER VMUTEL VMUTEC Min. -- 2.1 2.1 2.1 - 1.5 - 1.5 - 1.5 -- -- -- -- -- -- -- -- -- 70 70 70 66 70 70 35 35 35 -- -- -- 40 40 40 80 80 80 Typ. 35 2.5 2.5 2.5 0 0 0 0.01 0.01 0.1 35 35 35 3 3 3 78 78 78 71 78 78 50 50 50 -- -- -- 53 53 53 90 90 90 Max. 65 -- -- -- 1.5 1.5 1.5 0.1 0.1 0.3 70 70 70 10 10 10 -- -- -- -- -- -- 65 65 65 50 50 50 -- -- -- -- -- -- Unit mA Vrms Vrms Vrms dB dB dB % % % Vrms Vrms Vrms Vrms Vrms Vrms dB dB dB dB dB dB k k k dB dB dB dB dB dB VIN = 0Vrms THD = 1%( C ) THD = 1%( C ) THD = 1%(C ) VIN = 1Vrms, GVR = 20log (B / VIN) VIN = 1Vrms, GVL = 20log (B / VIN) VIN = 1Vrms, GVC = 20log ( B / VIN) VIN = 1Vrms VIN = 1Vrms VIN = 1Vrms Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO VIN = 1Vrms, CTR-L = 20log ( B R / B L) VIN = 1Vrms, CTR-C = 20log ( B R / B C) VIN = 1Vrms, CTL-R = 20log ( B L / B R) VIN = 1Vrms, CTL-C = 20log ( B L / B C) VIN = 1Vrms, CTC-R = 20log ( B C / B R) VIN = 1Vrms, CTC-L = 20log ( B C / B L) 50k x A (1 - A ) 50k x A fINL = 1kHz, VIN = 1Vrms, RINR = (1 - A ) 50k x A fINC = 1kHz, VIN = 1Vrms, RINR = (1 - A ) 1k x D fOUTR = 1kHz, ROUTR = 1- D fINR = 1kHz, VIN = 1Vrms, RINR = fOUTL = 1kHz, ROUTL = 1k x 1- 1k x fOUTC = 1kHz, ROUTC = 1- D D D D Conditions fRR = 100Hz, VRR RRR = 20log B VRR = 100mVrms, fRR = 100Hz, VRR RRR = 20log VRR = 100mVrms, B fRR = 100Hz, VRR RRR = 20log B VRR = 100mVrms, VIN = 1Vrms, VMUTER = 20log VIN = 1Vrms, VMUTEL = 20log VIN = 1Vrms, VMUTEC = 20log VIN B VIN B VIN B 8 Video ICs BH3866AS Parameter Volume attenuation, Rch Volume attenuation, Lch Volume attenuation, Cch Channel balance 1, RchLch Channel balance 1, RchCch Channel balance 1, LchCch Channel balance 2, RchLch Channel balance 2, RchCch Channel balance 2, LchCch Bass boost gain, Rch Bass boost gain, Lch Bass boost gain, Cch Bass cut gain, Rch Bass cut gain, Lch Bass cut gain, Cch Treble boost gain, Rch Treble boost gain, Lch Treble boost gain, Cch Treble cut gain, Rch Treble cut gain, Lch Treble cut gain, Cch AGC input / output level 1, Rch AGC input / output level 1, Lch AGC input / output level 2, Rch AGC input / output level 2, Lch AGC input / output level 3, Rch AGC input / output level 3, Lch AGC input / output level 4, Rch Symbol ATTMAXR ATTMAXL ATTMAXC CB1R-L CB1R-C CB1L-C CB2R-L CB2R-C CB2L-C VBMAXR VBMAXL VBMAXC VBMINR VBMINL VBMINC VTMAXR VTMAXL VTMAXC VTMINR VTMINL VTMINC VAGC1R VAGC1L VAGC2R VAGC2L VAGC3R VAGC3L VAGC4R Min. 80 80 80 - 1.5 - 1.5 - 1.5 - 2.0 - 2.0 - 2.0 13 13 13 - 18 - 18 - 18 9 9 9 - 15 - 15 - 15 0.7 0.7 50 50 90 90 160 Typ. 90 90 90 0 0 0 0 0 0 15.5 15.5 15.5 - 15.5 - 15.5 - 15.5 12 12 12 - 12 - 12 - 12 1 1 80 80 130 130 210 Max. -- -- -- 1.5 1.5 1.5 2.0 2.0 2.0 18 18 18 - 13 - 13 - 13 15 15 15 -9 -9 -9 1.4 1.4 110 110 170 170 260 Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Conditions VIN = 1Vrms, ATTMAXR = 20log VIN = 1Vrms, ATTMAXL = 20log VIN = 1Vrms, ATTMAXC = 20log VIN B VIN B VIN B BR VIN = 1Vrms, CB1R-L = 20log BL BR VIN = 1Vrms, CB1R-C = 20log BC VIN = 1Vrms, CB1L-C = 20log VIN = 1Vrms, CB2R-L = 20log VIN = 1Vrms, CB2R-C = 20log VIN = 1Vrms, CB2L-C = 20log Comparison with f = 100Hz, VIN = 100mVrms, bass flat Comparison with f = 100Hz, VIN = 100mVrms, bass flat Comparison with f = 100Hz, VIN = 100mVrms, bass flat Comparison with f = 100Hz, VIN = 100mVrms, bass flat Comparison with f = 100Hz, VIN = 100mVrms, bass flat Comparison with f = 100Hz, VIN = 100mVrms, bass flat Comparison with f = 10kHz, VIN = 100mVrms, treble flat Comparison with f = 10kHz, VIN = 100mVrms, treble flat Comparison with f = 10kHz, VIN = 100mVrms, treble flat Comparison with f = 10kHz, VIN = 100mVrms, treble flat Comparison with f = 10kHz, VIN = 100mVrms, treble flat Comparison with f = 10kHz, VIN = 100mVrms, treble flat BL BC BR BL BR BC BL BC mVrms VIN = 1mVrms mVrms VIN = 1mVrms mVrms VIN = 50mVrms mVrms VIN = 50mVrms mVrms VIN = 110mVrms mVrms VIN = 110mVrms mVrms VIN = 1Vrms 9 Video ICs BH3866AS Parameter AGC input / output level 4, Lch Symbol VAGC4L Min. 160 -- -- 4 4 0 0 1.5 1.5 7.5 7.5 - 6.5 1.5 4.7 -- 2 3.5 -- Typ. 210 0.4 0.4 6 6 1 1 4 4 10 10 -4 4 5 0 -- -- -- Max. 260 1 1 8 8 3.5 3.5 6.5 6.5 12.5 12.5 - 1.5 6.5 5.3 0.3 -- 5 0.9 Unit mVrms VIN = 1Vrms % % dB dB dB dB dB dB dB dB dB dB V V mA V V VIN = 200mVrms VIN = 200mVrms Conditions Total harmonic distortion at AGC ON, Rch THDAGCR Total harmonic distortion at AGC ON, Lch THDAGCL Max. surround gain, Rch . Max. surround gain, Lch Min. surround gain, Rch Min. surround gain, Lch Surround gain at Loop ON, Rch Surround gain at Loop ON, Lch Bass Add ON gain, Rch Bass Add ON gain, Lch Pseudo-stereo gain, Rch Pseudo-stereo gain, Lch DAC pin operating voltage 1 DAC pin operating voltage 2 Suction current at I2C BUS ACK SCL and SDA pin input high level SCL and SDA pin input low level VSUMAXR VSUMAXL VSUMINR VSUMINL VLPSUR VLPSUL VBAONR VBAONL VMONR VMONL VDAC1 VDAC2 IACK VIHI VILO VIN = 100mVrms, VSUMAXR = 20log B / VIN VIN = 100mVrms, VSUMAXL = 20log B / VIN VIN = 100mVrms, VSUMINR = 20log B / VIN VIN = 100mVrms, VSUMINL = 20log B / VIN VIN = 100mVrms, VLPSUR = 20log B / VIN VIN = 100mVrms, VLPSUL = 20log B / VIN f = 100Hz, VIN = 100mVrms, VBAONR = 20log B / VIN f = 100Hz, VIN = 100mVrms, VBAONL = 20log B / VIN VIN = 100mVrms, VMONR = 20log B / VIN VIN = 100mVrms, VMONL = 20log B / VIN The phases are the same between the input and output signal pins. 10 Video ICs BH3866AS *Measurement circuit 10k 47k 100 50 J 0.022 1 S7 21 2 S8 2 50k 0.039 I 0.022 Rg: 50 V 1 S1 VCC A 0.33 VCC RR 100 2 1 2 0.1 S5 10k 1 22 20k 25 470P 0.033 470P 0.033 2k 24 LT 23 LB 22 CT 21 CB 20 LOUT 19 COUT 18 SCV 17 DAC V S10 2 S11 2 5V 1 H 1 S4 0.1 1 5k 32 LIN 31 VCC 30 CIN 29 ADD 28 BIN 27 26 MSIN BGAIN STT 0.33 1 S2 BH3866AS 50k 2 A V Rg: 50 RIN 1 2 GND AGCADJ LS1 2 3 4 LS2 5 SOUT 6 PS 7 Vref 8 STB 9 RT 10 RB 11 ROUT 12 SRV 13 SLV 14 SCL 15 SDA 16 A G 5V 2k S3 VCC 18k 10 15k 4.7k I2C BUS serial input 0.1 100 470P E F 4.7 0.0056 1 0.1 0.033 V S6 V 100k 220k 1 2 S9 2 1 D 1k B C V Rg: 50 2.2 fOUT 2.2 V 10k THD Recommended attachments qElements marked with an asterisk BW = 400Hz ~ 30kHz Fig.1 * Carbon-sheathed resistors: 1% * Film capacitors: 1% * Ceramic capacitors: 1% wUnless otherwise noted, the following attachments should be used. Precautions concerning wiring qA bare ground should be used for GND. wThe wiring pattern of the I2C BUS should be separate from that of the analog unit, to avoid crosstalk. eParallel positioning of the SCL and SDA lines of the I2C BUS should be avoided wherever possible. If they are adjacent, they should be shielded. Slave address MSB LSB * Carbon-sheathed resistors: 5% * Film capacitors: 20% *Measurement circuit switch operation Parameter Quiescent circuit current Max. output voltage, Rch Max. output voltage, Lch Max. output voltage, Cch Voltage gain, Rch Voltage gain, Lch Voltage gain, Cch Symbol IQ VOMR VOML VOMC GVR GVL GVC 1 0 0 0 0 0 1 0 Measurement point I2C BUS SW NO. Selected address / data 1 2 3 4 5 6 7 8 9 10 11 0 0 0 1 0 2 0 3 0 4 0 5 0 6 1--1 1 1 1 1 1--1--F F F F F F 2 0 2 0 0 0 0C 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0 0 0 0C 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 2 1 1 2 1 1--0 0 0 0 FF 2 0 2 0 0 0 0C 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0 0 0 0C 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 2 1 1 2 1 1--0 0 0 0 FF 2 0 2 0 0 0 0C I B B B B B B 11 Video ICs Slave address MSB BH3866AS LSB 1 0 0 0 0 0 1 0 Parameter Total harmonic distortion, Rch Total harmonic distortion, Lch Total harmonic distortion, Cch Output noise voltage, Rch Output noise voltage, Lch Output noise voltage, Cch Residual noise voltage, Rch Residual noise voltage, Lch Residual noise voltage, Cch Crosstalk, RchLch Crosstalk, RchCch Crosstalk, LchRch Crosstalk, LchCch Crosstalk, CchRch Crosstalk, CchLch Input impedance, Rch Input impedance, Lch Input impedance, Cch Output impedance, Rch Output impedance, Lch Output impedance, Cch Ripple rejection, Rch Ripple rejection, Lch Ripple rejection, Cch Muting level, Rch Muting level, Lch Muting level, Cch Volume attenuation, Rch Volume attenuation, Lch Volume attenuation, Cch Channel balance 1, RchLch Channel balance 1, RchCch Channel balance 1, LchCch Channel balance 2, RchLch Channel balance 2, RchCch Channel balance 2, LchCch Bass boost gain, Rch I 2C BUS Measurement SW NO. Symbol Selected address / data point 1 2 3 4 5 6 7 8 9 10 11 0 0 0 1 0 2 0 3 0 4 0 5 0 6 THDR THDL THDC VNOR VNOL VNOC VMNOR VMNOL VMNOC CTR-L CTR-C CTL-R CTL-C CTC-R CTC-L RINR RINL RINC ROUTR ROUTL ROUTC RRR RRL RRC VMUTER VMUTEL VMUTEC 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0 0 0 0C 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 2 1 1 2 1 1--0 0 0 0 FF 2 0 2 0 0 0 0C 1 1 1 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0 0 0 0C 1 1 1 1 1 1 2 1 1 1--F F 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 1 1 1 2 1 1--0 0 0 0 FF 2 0 2 0 0 0 0C 1 1 1 1 1 2 1 1 1 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 1 1 2 1 1 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 1 1 1 2 1 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 1 2 1 1 1 2 1 1 1--F F F F 0 0 2 0 2 0 0 0 0C 1 1 2 1 1 1 1 2 1 1--0 0 FFFF 2 0 2 0 0 0 0C 1 1 1 2 1 2 1 1 1 1--F F F F 0 0 2 0 2 0 0 0 0C 1 1 1 2 1 1 1 2 1 1--F F 0 0 F F 2 0 2 0 0 0 0C 1 1 1 1 2 2 1 1 1 1--0 0 FFFF 2 0 2 0 0 0 0C 1 1 1 1 2 1 2 1 1 1--F F 0 0 F F 2 0 2 0 0 0 0C 1 2 2 1 1 1 1 1 1 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 2 1 2 1 1 1 1 1 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 2 1 1 2 1 1 1 1 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 1 2 1 1 2 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 1 1 2 1 2 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 1 1 1 1 1 1 1 2 2 1--0 0 0 0 0 0 2 0 2 0 0 0 0C 2 1 1 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0 0 0 0C 2 1 1 1 1 1 2 1 1 1--F F 0 0 0 0 2 0 2 0 0 0 0C 2 1 1 1 1 1 1 2 1 1--0 0 0 0 FF 2 0 2 0 0 0 0C 1 1 2 1 1 2 1 1 1 1--F F F F F F 2 0 2 0 0 0 0 E 1 1 1 2 1 1 2 1 1 1--F F F F F F 2 0 2 0 0 0 0 E 1 1 1 1 2 1 1 2 1 1--F F F F F F 2 0 2 0 0 0 0 E C C C B B B B C C B B B B B B A A A D D D B B B B B B B B B B B B B B B ATTMAXR 1 1 2 1 1 2 1 1 1 1 -- 0 0 0 0 0 0 2 0 2 0 0 0 0 C ATTMAXL 1 1 1 2 1 1 2 1 1 1 -- 0 0 0 0 0 0 2 0 2 0 0 0 0 C ATTMAXC 1 1 1 1 2 1 1 2 1 1 -- 0 0 0 0 0 0 2 0 2 0 0 0 0 C CB1R-L CB1R-C CB1L-C CB2R-L CB2R-C CB2L-C VBMAXR 1 1 2 2 1 2/ 1/ 1 1 1 -- F F F F 0 0 2 0 2 0 0 0 0 C 12 1 1 2 1 2 2/ 1 1/ 1 1 -- 0 0 F F F F 2 0 2 0 0 0 0 C 1 2 1112 1122 1121 1112 2 1 2/ 1/ 12 1 2/ 1/ 1 12 2 2/ 1 1/ 2 2 2 1 2/ 1/ 12 1 1--F F 0 0 F F 2 0 2 0 0 0 0C 1 1--3 3 3 3 0 0 2 0 2 0 0 0 0C 1 1--0 0 3 3 3 3 2 0 2 0 0 0 0C 1 1--3 3 0 0 3 3 2 0 2 0 0 0 0C 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 7 F 2 0 0 0 0C B 12 Video ICs BH3866AS Slave address MSB LSB 1 0 0 0 0 0 1 0 Parameter Bass boost gain, Lch Bass boost gain, Cch Bass cut gain, Rch Bass cut gain, Lch Bass cut gain, Cch Treble boost gain, Rch Treble boost gain, Lch Treble boost gain, Cch Treble cut gain, Rch Treble cut gain, Lch Treble cut gain, Cch AGC input / output level 1, Rch AGC input / output level 1, Lch AGC input / output level 2, Rch AGC input / output level 2, Lch AGC input / output level 3, Rch AGC input / output level 3, Lch AGC input / output level 4, Rch AGC input / output level 4, Lch I 2C BUS Selected address / data SW NO. Symbol 1 2 3 4 5 6 7 8 9 10 11 0 0 0 1 0 2 0 3 0 4 0 5 0 6 VBMAXL VBMAXC VBMINR VBMINL VBMINC VTMAXR VTMAXL VTMAXC VTMINR VTMINL VTMINC VAGC1R VAGC1L VAGC2R VAGC2L VAGC3R VAGC3L VAGC4R VAGC4L 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 7 F 2 0 0 0 0C 1 1 1 1 2 1 1 21 1--0 0 0 0 FF 7 F 2 0 0 0 0C 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 0 0 2 0 0 0 0C 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 0 0 2 0 0 0 0C 1 1 1 1 2 1 1 2 1 1--0 0 0 0 FF 0 0 2 0 0 0 0C 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 7 F 0 0 0C 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 2 0 7 F 0 0 0C 1 1 1 1 2 1 1 2 1 1--0 0 0 0 FF 2 0 7 F 0 0 0C 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 0 0 0 0 0C 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 2 0 0 0 0 0 0C 1 1 1 1 2 1 1 2 1 1--0 0 0 0 FF 2 0 0 0 0 0 0C 1 1 2 2 1 2 1 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 1 1 2 2 1 1 2 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 1 1 2 2 1 2 1 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 1 1 2 2 1 1 2 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 1 1 2 2 1 2 1 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 1 1 2 2 1 1 2 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 1 1 2 2 1 2 1 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 1 1 2 2 1 1 2 1 1 1--F F F F 0 0 2 0 2 0 0 0 0 1 Measurement point B B B B B B B B B B B B B B B B B B B C C B B B B B B B B B B H H G EF EF Total harmonic distortion at AGC ON, Rch THDAGCR 1 1 2 2 1 2 1 1 1 1 -- F F F F 0 0 2 0 2 0 0 0 0 1 Total harmonic distortion at AGC ON, Lch THDAGCL 1 1 2 2 1 1 2 1 1 1 -- F F F F 0 0 2 0 2 0 0 0 0 1 Max. surround gain, Rch Max. surround gain, Lch Min. surround gain, Rch Min. surround gain, Lch Surround gain at Loop ON, Rch Surround gain at Loop ON, Lch Bass Add ON gain, Rch Bass Add ON gain, Lch Pseudo-stereo gain, Rch Pseudo-stereo gain, Lch DAC pin operating voltage 1 DAC pin operating voltage 2 Suction current at I2C BUS ACK SCL and SDA pin input high level SCL and SDA pin input low level VSUMAXR 1 1 2 1 1 2 1 1 1 1 -- 0 0 F F 0 0 2 0 2 0 C F 0 0 VSUMAXL 1 1 1 2 1 1 2 1 1 1 -- F F 0 0 0 0 2 0 2 0 C F 0 0 VSUMINR VSUMINL VLPSUR VLPSUL VBAONR VBAONL VMONR VMONL VDAC1 VDAC2 IACK VIHI VILO 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0C0 0 0 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 2 0 2 0C0 0 0 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0D6 0 0 1 1 1 2 1 1 2 1 1 1--F F 0 0 0 0 2 0 2 0D6 0 0 1 1 2 1 1 2 1 1 1 1--0 0 FF 0 0 2 0 2 0 0 0 1 0 1 1 1 21 1 2 1 1 1--F F 0 0 0 0 2 0 2 0 0 0 1 0 1 1 2 2 1 2 1 1 1 1--F F F F 0 0 2 0 2 0 AF 0 0 1 1 2 2 1 1 2 1 1 1--F F F F 0 0 2 0 2 0 AF 0 0 1111111112100000020200020 1111111112200000020200000 1 1 1 1 1 1 1 1 1 1-- 1 1 1 1 1 1 1 1 1 1-- 1 1 1 1 1 1 1 1 1 1-- 13 Video ICs setting methods *Data BUS timing (1) I C 2 BH3866AS Parameter Clock frequency range The HIGH period of the clock THe LOW period of the clock SCL rise time SCL fall time Set-up time for start condition Hold time for start condition Set-up time for stop condition Time bus must be free before a new transmission can start Set-up time DATA Symbol FSCL tHIGH tLOW tr tf tsu; STA tHD; STA tsu; STO tBUF tsu; DAT Min. 0 4 4.7 -- -- 4.7 4 4.7 4.7 250 Typ. -- -- -- -- -- -- -- -- -- -- Max. 100 -- -- 1 0.3 -- -- -- -- -- Unit kHz s s s s s s s s ns t r t f SCL t LOW t HIG SDA start condition t SU; ST t HD; ST SDA stop condition t SU; ST t BUF SDA t SU; DA t HD; DA t t SU; STA = start code set-up time. HD; STA = start code hold time. t SU; STO = stop code set-up time. t t BUF = bus free time. SU; DAT = data set-up time. t HD; DAT = data hold time. Fig.2 Timing requirements for I2C BUS The above characteristics are logical values in the IC design, and are not guaranteed based on the shipping inspection. Any problems that may arise will be handled through mutual discussion in good faith. 14 Video ICs (2) I2C BUS format MSB S 1bit Slave Address 8bit LSB A 1bit MSB Selected Address 8bit LSB A 1bit MSB LSB Data 8bit A 1bit P 1bit BH3866AS * S = Start condition (recognition of start bit) * Slave Address = Recognition of IC. First 7 bits may consist of any data. The last bit must be LOW for writing purposes. * A = Acknowledge bit (recognition of recognition response) * Selected Address = Selection of volume, bass, treble, or matrix surround. * Data = Various items of volume and sound quality data. * P = Stop condition (recognition of stop bit) (3) Interface protocol 1) Basic format S MSB Slave Address LSB A Selected Address MSB LSB A Data MSB LSB A P 2) Auto increment (the selected address is incremented ( + 1) by the number of data) S MSB Slave Address LSB A Selected Address MSB LSB A Data 1, Data 2, ..., Data N MSB LSB A P (Examples) q Data 1 is set as the data of the address specified by the "Selected Address" parameter. w Data 2 is set as the data of the address specified by the "Selected Address" parameter + 1. e Data 3 is set as the data of the address specified by the "Selected Address" parameter + N. 3) Configuration which cannot be transmitted (in this case, only selected address 1 is set) S Slave Address MSB LSB A Selected Address 1 MSB LSB A Data MSB LSB A Selected Address 2 MSB LSB A Data MSB LSB A P CAUTION: If Selected Address 2 was sent as data following the data parameter, the contents will be recognized as data, and not as Selected Address 2. 15 Video ICs (4) BH3866AS slave address MSB A6 1 A5 0 A4 0 A3 0 A2 0 A1 0 A0 1 LSB R/W 0 BH3866AS The above slave address has been registered with Philips Corporation. (5) Selected addresses Set item 0 1 2 3 4 5 6 Lch volume Rch volume Cch volume Tone (bass) Tone (treble) Surround AGC MSB A7 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 Selected address A4 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 LSB A0 0 1 0 1 0 1 0 When sending continuous data, the auto increment function moves through the selected addresses in the following sequence. 0 1 2 3 4 5 6 16 Video ICs (6) Data Selected address Set item 00H 01H 02H 03H 04H 05H 06H Lch volume Rch volume Cch volume Tone (bass) Tone (treble) Surround AGC MSB A7 A6 A5 A4 Data A3 A2 A1 BH3866AS LSB A0 Lch Vol Rch Vol Cch Vol SON SSTE SMON DAC L / R / C Bass L / R / C Treble LOOP BASS Surround effect CSEL CON MUTE AGC Selected address Volume: 00H 02H all H: ATT 0dB all L: - (95dB) 1.0dB step level 03H 04H Bass / Tre: all H: Max. (FULL BOOST) all L: Min. (FULL CUT) Surr effect: (Broad gain adjustment) all H: Max. (15dB) all L: Min. (0dB) 1dB step 05H * LOOP * SSTE * SMON * SON * Mute * AGC 06H * BASS * CSEL * CON * DAC H: on / L: off H: on / L: off H: on / L: off H: on / L: off H: on / L: off H: on / L: off H: mix on / L: mix off H: C on / L: C off H: H out / L: L off H: H out / L: L out Contents Switch that varies the stage of the phase shift ON / OFF switch for (L - R) signal (stereo surround) ON / OFF switch for (L + R) signal (pseudo-stereo) ON / OFF switch for surround effect Muting switch AGC ON / OFF switch Low-pitch range mixing switch Selector switch for CIN input of COUT output or (L + R) signal Switch that selects whether or not COUT is output 0V or 5V output switch 17 Video ICs (7) Volume and amount of attenuation (reference examples) ATT (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 - 10 - 11 - 12 - 13 - 14 - 15 - 16 - 17 - 18 DATA (HEX) FF C4 AD 9F 93 8A 82 7B 75 6F 6A 66 61 5D 5A 56 53 50 4D ATT (dB) - 19 - 20 - 22 - 24 - 26 - 28 - 30 - 32 - 34 - 36 - 38 - 40 - 42 - 44 - 46 - 48 - 50 - 52 - 54 DATA (HEX) 4A 48 43 3E 3A 36 33 30 2D 2A 27 25 23 21 1F 1D 1B 19 18 ATT (dB) - 56 - 58 - 60 - 62 - 63 - 67 - 68 - 70 - 73 - 76 - 78 - 84 - BH3866AS DATA (HEX) 16 15 14 13 12 10 0F 0E 0D 0C 0B 09 00 CAUTION: The settings in the above table are reference values. When using them, make sure values are confirmed carefully before being set. 18 Video ICs (8) Bass and treble gain settings (reference examples) I2 C DATA (HEX) 7F 36 34 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 20 Bass Gain (dB) 15.9 15.2 14.3 13.0 12.2 11.3 10.4 9.3 8.0 6.7 5.3 4.0 2.9 1.8 1.1 0.0 Treble Gain (dB) 12.0 11.2 10.4 9.2 8.5 7.6 6.8 5.8 4.8 3.8 2.9 2.0 1.4 0.8 0.4 0.0 I2C DATA (HEX) 18 17 16 15 14 13 12 11 10 0F 0E 0D 0B 09 00 Bass Gain (dB) - 1.5 - 2.4 - 3.4 - 4.6 - 5.8 - 7.1 - 8.3 - 9.5 - 10.6 - 11.5 - 12.3 - 13.0 - 14.2 - 15.0 - 15.6 BH3866AS Step 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Step -1 -2 -3 -4 -5 -6 -7 -8 -9 - 10 - 11 - 12 - 13 - 14 - 15 Treble Gain (dB) - 0.8 - 1.3 - 2.0 - 2.8 - 3.7 - 4.7 - 5.7 - 6.6 - 7.5 - 8.3 - 9.0 - 9.6 - 10.6 - 11.3 - 11.8 Table 5: Tone microcomputer data (the gain value is given as a guide). CAUTION: (1) The gain values given in the table above for treble and bass data are the data when the filter constant is specified such that the peak and bottom values on the frequency characteristic diagram will be at the maximum and minimum gain levels. (2) The settings in the above table are reference values. When using them, make sure values are confirmed carefully before being set. 19 Video ICs BH3866AS *Application example 100k 0.022 10 + - VCC 10 10 10 100k 100k 0.012 10 0.039 47k 10k 10k 10 0.022 2k 4.7 470P 0.033 470P 0.033 10 10 4.7 100 32 LIN 31 VCC VCC 30 CIN 29 ADD 28 BIN 27 26 25 MIX OFF BASS 24 LT 23 LB 22 CT 21 CB 20 LOUT 19 COUT 18 SCV 17 DAC MSIN BGAIN 10k STT + - 50k CIN L+R 10k 50k + + Volume CSEL OFF Volume MIX ON SMON + 50k - Tone (bass / treble) + - 50k + - OFF Increment Volume Volume VCA ON A G C Increment Volume 50k OFF ON LOOP VCC - 1 2 VCC 50k 50k RIN 1 GND AGCADJ 2 3 LS1 4 LS2 5 SOUT 6 PS 7 Vref 8 STB 9 RT 10 RB 11 ROUT 12 0.0056 VCC 10 18k 15k 10 4.7 0.1 100k 220k 4.7k Units Resistance: Capacitance: F 100 4.7 470P 0.033 10 4.7 4.7 I2C BUS serial control Fig.3 *Operation notes supply voltage range (1) Operating power Within the operating power supply voltage range, operation of the basic circuit functions is guaranteed for the ambient operating temperature, but when using the product, be sure that settings for constants and elements, voltage settings, and temperature settings are carefully confirmed. (2) Operating temperature Within the recommended operating voltage range, operation of the circuit functions is guaranteed for the operating temperature range. Be aware that power dissipation conditions are related to the temperature. Also, except for conditions determined by electrical characteristics within this range, the rated values for electrical characteristics cannot be guaranteed, but the essential functions are maintained. (3) Application example We guarantee the application circuit design, but recommend that you thoroughly check its characteristics in actual use. If you change any of the external component values, check both the static and transient characteristics of the circuit, and allow sufficient margin in your selections to take into account variations in the components and ICs. Note that Rohm has not fully investigated patent rights regarding this product. 20 + VCA R-S - Tone (bass / treble) Volume + - - 10k ON AGC 10k L+S Tone (bass / treble) + - 10k OFF L+R L-R PHASE Surr effect LFP + OFF ON 10k ON 10k SHIFT - SSTE AMP SON 10k + - I2C BUS interface SCL SDA SRV 13 SLV 14 SCL 15 SDA 16 Video ICs (4) Bass filter for tone control VCC BH3866AS * Determining cutoff frequencies RB, LB, and CB pins R1 30k C1 25k 5k 1 1 = 2C1 x 30k 2C1R1 At a frequency of fC1, the LPF will be -3dB. fC1 = 1 2 VCC GND 1 2 VCC Fig.4 (5) Treble filter for tone control VCC HPF configuration RT, LT, and CT pins R2 30k C2 1 2 VCC GND (6) Setting the AGC level The AGC level is set by the voltage divider between voltage VCC and GND. A gain of 0dB voltage should be used in the range of 100mVrms to 400mVrms. 10 VCC = 9V AGCADJ voltage = 4.1V LR common-mode input Gain 0dB voltage OUTPUT VOLTAGE (Vrms) 1 AGC off 0.1 Gain 0dB voltage (Vrms) AGC on 0.01 0.001 0.001 0.01 0.1 1 10 INPUT VOLTAGE (Vrms) Fig. 6 (Reference data) AGC characteristic + - + - + + - LPF fC2 = 1 1 = 2C2 x 30k 2C2R2 Fig.5 600 VCC = 9V LR same-phase input 500 400 300 200 100 0 2 2.5 3 3.5 4 4.5 5 AGCADJ VOLTAGE (V) [3pin] Fig. 7 (Reference data) Relation between AGCADJ voltage and gain 0dB voltage 21 Video ICs (7) Determining the external LS1 (pin 4) and LS2 (pin 5) for the AGC BH3866AS (8) Attachment of external SOUT (pin 6) of surround section L.P.F. 10k R1 0.0056 430 R01 4.7k 4 LS1 C1 10 Amplifier which determines level of surround effect RL1 100k R2 C SOUT 6 Fig.10 Fig.8 Suppressing phase detecting circuit f1 = f2 = 1 2CR2 * Attack time: R01 x C1 * Recovery time: RL1 x C1 1 2C (R1 + R2) R2 A1 = R1 + R2 A2 = 1 20k R02 Gain (dB) A2 5 LS2 C2 4.7 A1 RL2 220k f2 f1 Frequency (Hz) Fig.9 Amplifying phase detection circuit Fig.11 * Attack time: R02 x C2 * Recovery time: RL2 x C2 (9) External PS (pin 7) of the phase shifter 18k R2 18k R3 The attack and recovery times should be determined based on the internal resistors in the IC and on the external capacitor and resistor. The internal resistors are R01 = 430 and R02 = 20k (Typ.). Reducing the constant of the C2 capacitor of LS2 shifts the point where amplification begins in the direction of a lower input voltage. The distortion ratio changes as well, in the direction of worse distortion. Reducing the constant of the C1 capacitor of LS1 causes worse distortion. Increasing the resistance value of RL1 causes the amount of suppression to decrease. - + R1 18k 7 C1 0.1 Fig.12 The resistance in the IC is 18k (Typ.). = -2tan-1 (2fR1C1) 22 + - + - Video ICs (10) Surround and pseudo-stereo effects 1) Surround t: Time of delay caused by phase shifter P: Amount attenuated at phase shifter stage E: Amount of surround effect Lch 32 t x P xE BH3866AS + + + 20 LOUT = L + t (L - R) EP L-R Phase shifter Effect adjustment LPF - Rch 1 + + 12 ROUT = R + t (R - L) EP Fig.13 2) Pseudo-stereo effect Lch 32 t x P xE + + + 20 LOUT = L + t (L + R) EP L+R BPF Configured externally Phase shifter Effect adjustment LPF - Rch 1 + + 12 ROUT = R - t (L + R) EP Fig.14 28 (11) The level of the surround effect The level of the surround effect can be varied between 0 and 15dB, using I2C BUS data. Please be aware, however, that this gain is not the total gain between input and output. In precise terms, it specifies the effect level control range of the surround signal for the SOUT pin. (With single-side input and the stereo / surround effects: VCC = 9V, f = 1kHz, VIN = 100mVrms, Ta = 25C.) 50k 10k 1 2 VCC 26 R1 10 Gain = 20log 10k + R1 R1 + The internal blocks in the IC for the surround and pseudo-stereo effects are configured as shown above. The feeling of the surround location and the stereo feeling of the pseudo-stereo effect can be changed by varying the amount of the effect. Also, the loop switch can be turned on to create a pseudo-increase in the number of phase shifter stages. Raising the gain of the effect level with the loop switch on causes instability, however, so the level of the effects should be kept at around 6dB or below. In order to prevent a popping sound when switching between the surround and pseudo-stereo effects, the switch on the stereo surround side of the SSTE should be left in the ON position. (12) Pin 17 (DAC) output Setting the DAC command for the I2C BUS to HIGH enables 5V output, and setting it to LOW enables 0V output. (13) BASS command Creating an external LPF with the signals (L + R) output from ADD (pin 29) and inputting those signals to BIN (pin 28) enables configuration of a low-pitch amplification circuit. This switch serves as the I2C BUS bass command. The gain for the amplifier can be set through the external resistance, using BGAIN (pin 26). BIN - BASS SW Fig.15 23 Video ICs (14) The necessity for Cch and the application If there are only a left and right speaker, moving slightly to the left or right of the television set causes a difference in the sound paths, and a characteristic trough from 500Hz to 2kHz is created by the ensuing interference, producing a muffled or contained sound. Also, listeners positioned to the left or right hear the sounds from the closest speaker causing the positions of the image and sound to not match. Due to their setup, low-pitched sounds are produced more easily from the left and right speakers. However, in front of the speakers, because the placement of the speakers directs the sound in a cone-shaped direction, traveling along the sides of the television, a "port" effect results and the sound becomes muffled. To solve this problem, a center speaker is provided, and assuming this speaker is attached directly to the center grille, the orientation and clarity are improved significantly. Also, as a center channel application, this can be used to adjust the microphone mixing level, enabling use of the set as a karaoke set. (15) Noise when the step is switched In the application circuit example, using the SRV, SLV, SCV, STB, and STT pins as an example, constants are provided for each. These constants change depending on the signal level setting, the mounting wiring pattern, and other factors. Careful consideration should be given to the constants before they are determined. An internal equivalent circuit is shown below. (A primary integration circuit is set, so that changes are implemented slowly.) R Each pin BH3866AS within seven bits (64 + 1 step). (17) I2C BUS control High-frequency digital signals are input to the SCL and SDA pins, so the wiring and wiring patterns must be arranged in such a way that they do not interfere with the analog signal system line. (18) Power On Reset When the power supply is turned on, an internal circuit carries out an initialization within the IC. When the power supply is turned on, the volume levels of the left, right, and center channels are set to - , and the DAC output (pin 17) is set to 0V. Once it has been turned on, if the power supply is turned off and then immediately turned on again, if there is any residual load on the capacitor, there may be cases when the status described above does not occur. If this happens, operation should be carried out with the muting function on, until an I2C BUS command is transmitted. (19) Vref (pin 8) capacitor A capacitance of 100F is recommended for the power supply filter attached to VREF. If this capacitance is set too low, the minimum attenuation level of the volume deteriorates. Crosstalk also tends to deteriorate. The IC contains internal pre-charge and discharge circuits for the capacitor attached to Vref. (20) Excessive input Steps have been taken with this product to avoid a situation in which, if a signal is input which exceeds the maximum input voltage for the LIN, RIN, and CIN pins, a rebound waveform is produced even if hard clipping of the output signal is implemented. Consequently, there is no need to worry that the listener will hear distorted sound because of a rebound waveform. (21) Request concerning the fundamental design Due to its pin layout, it is difficult to remove crosstalk from the left channel to the center channel in this IC. This is because the output signal at LOUT (pin 20) overlaps the capacitance coupling of CB (pin 21) and CT (pin 22). This should be given adequate consideration in the fundamental design of the set, when the pattern is laid out. The following illustration shows an example of countermeasures. LOUT 19 C 10 Lch output + C 0.033 C 470p CB 20 CT 21 C (External) Fig.16 SRV, SLV, SCV, STB, STT (16) Level settings for volume and tone In this databook, values are noted for the control serial data in relation to the amount of attenuation or gain, as reference values. Since the internal D / A converter is configured on the R-2R system, data exists in locations where there are no continuous changes between one item of data and the next. This can be used where detailed settings are required. However, the volume must be set within eight bits (256 steps), and the tone 24 + - R value (k) 30 Video ICs (22) Relation with the BH3865S The BH3866AS and BH3865S are pin compatible, and share some of the same selected address and data parameters for the I2C BUS. Therefore, the same substrates and software can be shared at the product planning stage. BH3866AS *Electrical characteristic curves TOTAL HARMONIC DISTORTION: THD (%) 50 QUIESCENT CURRENT: IQ (mA) 45 40 35 30 25 20 15 10 5 0 5 6 7 8 9 10 POWER SUPPLY VOLTAGE: VCC (V) 1 0.5 OUTPUT VOLTAGE: VOUT (dBV) VCC = 9V f = 1kHz +0 -4 -8 - 12 - 16 - 20 - 24 - 28 - 32 - 36 10m 100m 1 - 40 10 100 1k 10k 100k During cut VCC = 9V VIN = 100mVrms During boost 0.1 0.05 0.01 INPUT VOLTAGE: VIN (Vrms) FREQUENCY: f (Hz) Fig. 17 Quiescent current vs. power supply voltage Fig. 18 Total harmonic distortion vs. input voltage Fig. 19 Output gain vs. frequency *External dimensions (Units: mm) 28.0 0.3 32 17 8.4 0.3 1 0.51Min. 16 10.16 3.2 0.2 4.7 0.3 0.3 0.1 1.778 0.5 0.1 0 ~ 15 SDIP32 25 |
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